1. Field of the Invention
The present invention relates generally to nitride read only memory (NROM) devices, and more particularly, to a NROM erase system and method for over erase reduction during an erase operation.
2. Description of the Related Art
Nitride read only memories (NROM) are nonvolatile memories in which a single NROM cell can be electrically programmed and a large number of NROM cells —called a sector—are electrically erasable at the same time. There are three basic operations for a NROM device: read (a byte or a word), program (a byte or a word), erase (one or more sectors).
To erase a single sector for a NROM device, a high electric field must be applied between the sources and the gates of the NROM cells belonging to the sector to allow for Fowler-Nordheim current to discharge the floating gates of the NROM cells. This task is accomplished by applying a high voltage (in the range of 12V) to the sources of the NROM cells to be erased while grounding their gates (source erase), or by splitting the biasing voltage between sources and gates of the NROM cells to be erased (negative gate erase).
The erase operation of a NROM device is more complicated than the read and program operations because the erase operation is performed on an entire sector. An erase operation comprises at least one erase process and at least one verification process. Due to the fact that each NROM cell of a sector processes different erasing ability, multiple erase processes might be needed for an erase operation in order to erase all the NROM cells of the sector. A verification process is performed after an erase process is finished during the erase operation.
At the beginning of the erase operation, an initial erase voltage pulse is applied to all the NROM cells belonging to the sector to be erased. A verification process of the erase operation is followed to verify whether all the NROM cells of the sector are erased after the erase process of the erase operation. If the verification process is failed for at least one NROM cell of the sector, a higher erase voltage pulse is applied to all the NROM cells of the sector to erase the remaining un-erased NROM cells. Another verification process is performed to verify whether all the NROM cells of the sector are erased. If some of the NROM cells still remain un-erased, the erase processes and the verification processes will continue until all the NROM cells of the sector are erased. For an erase process, the erase voltage pulse for a subsequent erase process is higher than the erase voltage pulse for a previous erase process. The increase of the erase voltage pulse for each subsequent erase process is about 400 mV. Because the erase voltage pulse is applied to the entire sector during the multiple erase processes, the NROM cells erased by a previous erase process will become over-erased during subsequent erase processes.
FIG. 1 is a threshold voltage distribution graph 100 showing the threshold voltage Vt distribution of the erased NROM cells of a sector after an erase operation. The threshold voltages of the erased sector are distributed between the high threshold voltage VEH and the low threshold voltage VEL. As indicated, the threshold voltage distribution graph 100 is crooked near the VEL, which is caused by the over-erased NROM cells of the sector after multiple erase processes during an erase operation. The over erase for the NROM cells also causes the threshold voltages of those over-erased NROM cells to be too low.
In view of the foregoing, there is a need for improvement upon conventional NROM erase systems and methods in order to prevent the NROM cells of a sector from being over-erased.